The present invention relates to a semiconductor apparatus including an MOS structure and a semiconductor device having an impurity concentration higher than a channel region of the MOS structure, and also relates to a method of manufacturing such a semiconductor apparatus.
As disclosed in JP-A 60-74678, for example, a thyristor and a TRIAC in which an MOS structure is compounded have hitherto been known. FIG. 1 shows an example of the structure of a semiconductor apparatus including a thyristor having the MOS structure. In this case, the planar type is assumed. The semiconductor apparatus shown in FIG. 1 includes thyristor 11 and MOS transistor 12 for short-circuiting gate G and cathode K of thyristor 11. Thyristor 11 comprises: N-type emitter region 13; a P-type base region 14; N-type base region 15; and P-type emitter region 16. On the other hand, MOS transistor 12 comprises: N-type source region 17; N-type drain region 18; gate insulative film 19; and gate electrode 20. MOS transistor 12 is formed in P-type well region 21. P-type well region 22, for driving the gate of MOS transistor 12, is surrounded by guard ring 23a.
To obtain the desired characteristics in the foregoing constitution, the surface impurity concentration of P-type base region 14 of thyristor 11 must be set to approx. 2.times.10.sup.17 cm.sup.-3, and the surface impurity concentration of P-type well region 21, in which MOS transistor 12 is formed, must be set to approx. 5.times.10.sup.16 cm.sup.-3. Thus, it is necessary to form P-type regions 14 and 21 having surface impurity concentrations different from each other, and the impurities must be implanted and diffused into each of these regions in different steps. Therefore, as can be clearly seen, there are drawbacks to the present method of manufacturing this type of semiconductor device, such as the increased complexing of the manufacturing process, along with the inevitable increase in manufacturing cost and the reduction in yield.
FIGS. 2A to 2G show several of the steps involved in the manufacture of a thyristor including an MOS structure with much attention to the formation of P-type regions 14 and 21. First, as is shown in FIG. 2A, in relatively thick oxide film 24 formed on N-type base region 15, the portion corresponding to the region where P-type base region 14 will be formed is etched to thereby form opening 25. Next, as is shown in FIG. 2B, buffer oxide film 26 whose thickness is about 1000 .ANG. is formed on N-type base region 15 exposed in opening 25. Then, P-type impurities are ion implanted into base region 15, through oxide film 26, to a predetermined concentration. Thereafter, a heat treatment is performed, and the P-type impurities are annealed and diffused, thereby forming P-type impurity layer 14A serving as P-type base region 14, as shown in FIG. 2C.
Next, as is shown in FIG. 2D, the portion corresponding to oxide film 24, on the region where P-type well region 21 of MOS transistor 12 will be formed, is etched to thereby form opening 27. Buffer oxide film 28 is formed on the exposed surface of N-type base region 15 in opening 27. After buffer oxide film 28 has been formed there, buffer oxide film 26 grows thickly. P-type impurities are implanted into base region 15 through only buffer oxide film 28. The dose amount at this time is set to a value lower than that used in formation of P-type impurity layer 14A. Next, a heat treatment is performed to diffuse and annel the P-type impurities. As a result, as is shown in FIG. 2E, the impurities in P-type impurity layer 14A are deeply diffused and P-type impurity layer 14A serves as P-type base region 14. After this, P-type well region 21 is formed.
After buffer oxide film 28 has been removed (this film may be left and used as a gate oxide film without removing), as is shown in FIG. 2F, gate oxide film 19 is formed, with gate electrode 20 being formed thereon. Thereafter, N-type impurities are ion implanted, using gate electrode 20 and oxide film 24 as masks, after which annealing and diffusing are performed. As a result, as can be seen in FIG. 2G, source region 17 and drain region 18 are formed in P-well type region 21.
The foregoing manufacturing method does, however, have drawbacks, such as that the manufacturing steps are complicated and the overall manufacturing process, therefore, time-consuming, and that it is difficult to control the surface impurity concentrations, diffusion depths, and the like of P-type base region 14 and P-type well region 21.